Approximation of hardware accelerators employing machine-learning models
(Assistant Professor, Department of Computer Systemsratory,Brno University of Technology, Czech Republic)
Bio: Vojtech Mrazek received a M.Sc. and Ph.D. degrees in information technology from the Faculty of Information Technology, Brno University of Technology, Czech Republic, in 2014 and 2018. He is a assitant professor at the Faculty of Information Technology with Evolvable Hardware Group and he was also a visiting post-doc researcher at Institute of Computer Engineering, Technische Universität Wien (TU Wien), Vienna, Austria (2018-2019). His research interests are approximate computing, genetic programming and machine learning. He has authored or co-authored over 45 conference/journal papers focused on approximate computing and evolvable hardware. He received several awards for his research in approximate computing, including the Joseph Fourier Award in 2018 for research in computer science and engineering.
Abstract:The goal of this tutorial will be to introduce functional hardware approximation techniques employing machine learning techniques. Functional approximation changes the function of a circuit slightly in order to reduce its power consumption. Machine learning models can help to estimate the error and the resulting circuit power consumption. The use of these techniques will be presented at multiple levels - at the individual component level in the transition from ASICs to FPGAs and at the higher level of HW accelerator synthesis.
Leticia Maria Bolzani Poehls
RRAMs: How to Guarantee Their Quality After Manufacturing?
(Senior Researcher, RWTH Aachen University, Germany )
Bio: Leticia Maria Bolzani Poehls graduated in Computer Science at the Federal University of Pelotas (Brazil) in 2001 and received the best thesis award for her work. In the year 2004 she received her Master of Science Degree in Electrical Engineering at Pontifical Catholic University of Rio Grande do Sul (Brazil). During her Ph.D. her work was focused on the development of New Techniques for Highly Reliable Systems-on-Chip. In 2008 she received her Ph.D. in Computer Engineering from the Politecnico di Torino (Italy). She holds three postdoctoral titles, the first one accomplished in 2008 in the field of Low Power Design of Integrated Circuits (ICs) at the Politecnico di Torino, the second one in 2010 with focus on Electromagnetic Interference-Aware Systems-on-Chip Design at the Catholic University of Rio Grande do Sul (Brazil), and the third form the Politecnico di Torino (Italy) achieved in 2013 in the area of emerging technologies. From 2010 to 2022 she was Professor of the School of Technology of the Catholic University of Rio Grande do Sul and part of the EASE research laboratory, leading the OASiS research group. Currently, she is a senior researcher at RWTH Aachen University working on test and reliability of memristive devices, more specifically she is working to develop new fault models and manufacturing testing strategies for Resistive RAMs as well fault tolerance approaches for memristor-based circuits and systems. Her fields of interest basically include test & fault tolerance of CMOS-based integrated systems, including emerging technologies, power-, aging- and temperature-aware integrated circuit design, and Electronic Design Automation (EDA) tools for optimization of integrated circuits. Among other activities, she serves as technical committee member in many IEEE-sponsored conferences. She is further member of the Steering Committee for the IEEE Latin American Test Symposium and the Biannual European - Latin American Summer School on Design, Test and Reliability (BELAS). Since 2016 she is Coordinating Editor of Journal of Electronic Testing: Theory and Application.
Abstract: Memristive devices represent promising candidates to complement and/or replace CMOS technology due to their CMOS manufacturing process compatibility, great scalability, high density, zero standby power consumption as well as their capacity to implement high density memories and new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing deviations, defects and process variation, that may cause unique faulty behaviors that are not seen in CMOS, significantly increasing the complexity of test strategies. In this context, this tutorial aims to provide an overview of possible manufacturing deviations, their faulty behavior as well their impact on the reliability of Resistive Random-Access Memories (RRAMs) during lifetime. As final topic, I will summarize the state-of-the-art related to manufacturing test strategies, including aspects related to the use of stress conditions to facilitate fault detection.