DDECS 2023 Tallinn, Estonia
26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
May 3-5, 2023
Tallinn, ESTONIA


Schedule at a glance


DDECS Programme Booklet


Detailed Programme

Wednesday, May 3

08:30    Registration

09:00    Opening Session

09:30    Keynote 1
             Moderator: Maksim Jenihhin

  • Reconfigurable Computing for Software Programmers?
    Paolo Ienne, Architecture Laboratory, EPFL, Switzerland

10:15    Session 1: FPGAs and Virtual Prototyping
             Session chair: Lukáš Sekanina

  • Evaluating the Hardware Performance Counters of Xtensa Virtual Prototype.
    Adebayo Omotosho1, Sirine Ilahi2, Ernesto Cristopher Villegas3, Christian Hammer2, Christian Sauer3
    University of Central Lancashire, United Kingdom; 2University of Passau, Germany; 3Cadence Design Systems, Germany
  • Optimizing Packet Classification on FPGA.
    Michal Kekely, Jan Korenek
    Brno University of Technology, Czech Republic
  • Active Wire Fences for Multi-Tenant FPGAs.
    Ognjen Glamocanin, Andela Kostic, Stasa Kostic, Mirjana Stojilovic
    EPFL, Switzerland

11:30    Coffee break

11:45    Session 2: Test Generation and Built-In Self-Test
             Session chair: Artur Jutman

  • Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoC with delay faults.
    Paolo Bernardi1, Gabriele Filipponi1, Matteo Sonza Reorda1, Davide Appello2, Claudia Bertani2, Vincenzo Tancorre2 1Politecnico di Torino, Italy; 2STMicroelectronics, Italy
  • Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree Models.
    Swantje Plambeck, Goerschwin Fey
    Hamburg University of Technology, Germany
  • Reducing Output Response Aliasing Using Boolean Optimization Techniques.
    Robert Hülle, Petr Fišer, Jan Schmidt
    Czech Technical University in Prague, Czech Republic

13:00    Lunch

14:00    Session 3: Deep Learning Applications and Design
             Session chair: Zainalabedin Navabi

  • Split-Et-Impera: A Framework for the Design of Distributed Deep Learning Applications.
    Luigi Capogrosso, Federico Cunico, Michele Lora, Marco Cristani, Franco Fummi, Davide Quaglia
    University of Verona, Italy
  • Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits.
    Michal Pinos, Vojtech Mrazek, Lukas Sekanina 
    Brno University of Technology, Czech Republic
  • NeuroPIM: Flexible Neural Accelerator for Processing-in-Memory Architectures.
    Ali Monavari1, Sepideh Fattahi1, Hossein S. A. Rezaei1, Mehdi Modarressi1, Masoud Daneshtalab2
    1University of Tehran, Iran; 2MDU, Sweden

15:15    Poster Session (with Coffee)
             Session chair: Mahdi Taheri

P.1  Hardware Acceleration of FHEW.
Jonas Bertels, Michiel Van, Furkan Turan, Ingrid VerbauwhedeCOSIC, KU Leuven, Belgium

P.2  Supporting analog design for reliability by efficient provision of reliability information to designers.
Fabio A. Velarde Gonzalez1, Lukas Hahne1, Katrin Ortstein1, André Lange 1, Sonja Crocoll2
Fraunhofer Institute for Integrated Circuits
, Germany; 2X-FAB Dresden GmbH & Co. KG, Germany

P.3  Characterization of Interconnect Fault Effects in SRAM-based FPGAs.
Christian Fibich1, Martin Horauer1, Roman Obermaisser2
UAS Technikum Wien, Austria;
2University of Siegen, Germany

P.4  LUTIC: A CRAM-based Architecture for Power Failure Resilient In-Memory Computing.

Khakim Akhunov, Kasim Sinan Yildirim
University of Trento, Italy

P.5  Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes.
Rune Krauss1, Mehran Goli1, Rolf Drechsler1,2
1University of Bremen, Germany; 2DFKI, Germany

P.6  High-Throughput Approximate Multiplication Models in PyTorch.
Elias Trommer1,2, Bernd Waschneck1, Akash Kumar2
1Infineon Technologies, Germany; 2Technische Universität Dresden, Germany

P.7  A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators.
Nooshin Nosrati, Zainalabedin Navabi
University of Tehran, Iran

P.8  HermesBDD: A Multi-Core and Multi-Platform Binary Decision Diagram Package.
Luigi Capogrosso, Luca Geretti, Marco Cristani, Franco Fummi, Tiziano Villa
University of Verona, Italy

IP.a Acceleration of Attribute-based Encryption by a Dedicated Hardware.
Anawin Opasatian, Makoto Ikeda
University of Tokyo, Japan

IP.b Standard Cells with Inverted Inputs in 7nm Technology.
Tung-Chun Wu, Rung-Bin Lin
Yuan Ze University, Taiwan

16:15    Embedded Tutorial 1
             Session chair: Wolfgang Ecker

  • Approximation of hardware accelerators employing machine-learning models.
    Vojtech Mrázek, Brno University of Technology, Czech Republic

17:15    Free time

18:00    Welcome Reception


Thursday, May 4

08:30    Registration

09:00    Keynote 2
Moderator: Nele Mentens

  • Quantum-secure Systems and Circuits 
    Johanna Sepúlveda, Airbus Defence and Space - Intelligence, Germany

09:45    Session 4: Secure Implementation and Analysis
             Session chair: Fabian Vargas

  • Structured Design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations. 
    Carl Riehm1, Christoph Frisch1, Florin Burcea1, Matthias Hiller2, Michael Pehl1, Ralf Brederlow1
    1Technical University of Munich, Germany; 2Fraunhofer AISEC, Germany
  • Counterfeit Chip Detection using Scattering Parameter Analysis.
    Maryam Saadat Safa, Tahoura Mosavirik, Shahin Tajik
    Worcester Polytechnic Institute, USA

10:35    Coffee

10:45    Session 5: Hardware Security
Session chair: Mirjana Stojilovic

  • Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques.
    Marcel Merten1, Muhammad Hassan1,2, Rolf Drechsler1,2
    1University of Bremen, Germany; 2DFKI, Germany
  • A Digital Delay Model Supporting Large Adversarial Delay Variations.
    Daniel Öhlinger, Ulrich Schmid
    Technische Universität Wien, Austria
  • A Lightweight Intrusion Detection System against IoT Memory Corruption Attacks.
    Mohamed El Bouazzati1, Russell Tessier2, Philippe Tanguy1, Guy Gogniat1
    1Université Bretagne Sud (Lab-STICC), France; 2University of Massachusetts, USA

12:00    Student Session: Design and Analysis of Hardware
             Session chair: Petr Fišer

  • APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors.
    Mahdi Taheri1, Mohammad Hasan Ahmadilivani1, Maksim Jenihhin1, Masoud Daneshtalab1,2, Jaan Raik1
    1Tallinn University of Technology, Estonia; 2Mälardalen University, Sweden
  • A Configurable Mixed-Precision Convolution Processing Unit Generator in Chisel.
    Jure Vreca, Anton Biasizzo
    Jo┼żef Stefan Institute, Slovenia
  • Open Automation Framework for Complex Parametric Electrical Simulations.
    Sergio Vinagrero Gutierrez1, Pietro Inglese1, Giorgio Di Natale2, Elena Ioana Vatajelu2
    1TIMA Laboratory, France; 2CNRS, France
  • A Low-Cost Combinational Approximate Multiplier. 
    Zahra Hojati, Zainalabedin Navabi
    University of Tehran, Iran

13:00    Lunch

14:00    Special Session: Bits, Flips and RISCs
             Organizers: Milos Krstic, Wolfgang Ecker
             Session chair: Rolf Drechsler

  • Design and Verification of Resilient RISC-V Processor - TETRISC Approach.
    Fabian Vargas, Li Lu, Anselm Breitenreiter, Junchao Chen, Markus Ulbricht, Milos Krstic
    IHP - Leibniz Institute for High Performance Microelectronics, Germany
  • Automated Hardening and Analysis of RISC-V Cores.
    Wolfgang Ecker, Sebastian Siegfried Prebeck, Endri Kaja, Nicolas Gerlin, Ares Tahiraga
    Infineon Technologies, Germany
  • Safety development and verification flow for RISC-V cores.
    Maribel Gomez, Eyck Jentzsch
    MINRES Technologies, Germany

15:00    Short break (grab refreshments)

15:05    Panel: AI at the edge: will technology and architectures get us there faster?
             Organizer and Moderator: Elena-Ioana Vatajelu

  • Rolf Drechsler, University of Bremen and DFKI, Germany
  • Leticia Maria Bolzani Poehls, RWTH Aachen University, Germany
  • Lukas Sekanina, Brno University of Technology, Czech Republic
  • Zainalabedin Navabi, University of Tehran, Iran

16:20    Free time

17:00    Social Event


Friday, May 5

08:30    Registration

09:00    Keynote 3
Moderator: Jaan Raik

  • Autonomous vehicles - the state-of-play, challenges, and opportunities. 
    Daniel Watzenig, Virtual Vehicle Research Center Graz, Austria

09:45    Industrial presentation

10:30    Coffee

11:15    Session 6: Biotech and Healthcare Systems
             Session chair: Hana Kubátová

  • Standalone Area Optimized ASIC Tag Powered and Programmable by Light for Identification of Novel Drug Candidates.
    Dominic Korner, Andreas Kramer, Klaus Hofmann, Felix Hausch
    TU Darmstadt, Germany
  • MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers.
    Martin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukas Sekanina
    Brno University of Technology, Czech Republic
  • Verifying Bio-Electronic Systems.
    Joseline Heuer1, Rene Krenz-Baath1, Roman Obermaisser2
    1Hochschule Hamm-Lippstadt, Germany; 2University of Siegen, Germany

12:00    Embedded Tutorial 2
Session chair: Witold Pleskacz

  • RRAMs: How to Guarantee Their Quality After Manufacturing? 
    Leticia Maria Bolzani Poehls, RWTH Aachen University, Germany

13:00    Lunch

14:00    Session 7: Reliable Design of Deep Learning Accelerators
             Session chair: Leticia Bolzani Pöhls

  • A Reliability-aware Environment for Design Exploration for GPU Devices.
    Robert Alexander Limas Sierra, Juan David Guerrero Balaguera, Josie Esteban Rodriguez Condia, Matteo Sonza Reorda
    Politecnico di Torino, Italy
  • A Comprehensive Analysis of Transient Errors on Systolic Arrays.
    Eleonora Vacca, Sarah Azimi, Luca Sterpone
    Politecnico di Torino, Italy
  • Resilence-Performance Tradeoff Analysis of a Deep Neural Network Accelerator.
    Salvatore Pappalardo1, Annachiara Ruospo2, Ian O'Connor1, Bastien Deveautour1, Ernesto Sanchez2, Alberto Bosio1
    1École Centrale de Lyon, France; 2Politecnico di Torino, Italy

15:15    Closing Session

15:45    Farewell



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