DDECS 2023 Tallinn, Estonia
26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
May 3-5, 2023
Tallinn, ESTONIA

Special Session


"Bits, Flips and RISCs"


  • Milos Krstic, IHP - Leibniz Institute for High Performance Microelectronics, DE
  • Wolfgang Ecker, Infineon Technologies, DE


Design and Verification of resilient RISC-V Processor - TETRISC Approach

Fabian Vargas, Li Lu, Anselm Breitenreiter, Junchao Chen, Markus Ulbricht, Milos Krstic, IHP - Leibniz Institute for High Performance Microelectronics, DE

Abstract: The integration of flexible mitigation measures and robust system status monitoring is essential for enhancing the reliability of ICs in complex operating environments. One of the important challenges of processor-based architectures is also reliability verification, where some novel methods based on the use of AI could be applied to reduce the verification time. On the architectural side, a highly reliable resilient multiprocessing system, named TETRISC (TETra Core System based on RISC-V) SoC, has been proposed to address the dynamic reliability adjustment of the system in harsh environments, while simultaneously monitoring multiple fault sources. The TETRISC SoC is a quad-core multiprocessing platform that utilizes the open-source PULPissimo single-core architecture. The TETRISC SoC chip is fabricated using IHP 130 nm technology and utilizes a standard cell library for four RISC-V cores, with a rad-hard cell library employed for the remainder of the design. The tests of the chip are currently ongoing and the architecture of the chip and preliminary results will be discussed.

Automated Hardening and Analysis of RISC-V Cores

Wolfgang Ecker, Sebastian Siegfried Prebeck, Endri Kaja, Nicolas Gerlin, Ares Tahiraga, Infineon Technologies, DE

Abstract: More and more applications such as automotive, space, avionics, or industrial require chip hardening. Being particles, electro-magnetic pulses, electro-migration or other threats as a risk for faults, the chips must work safely or even fully operational if an error occurs, e.g. one of the stored bits flips or the computed values are wrong. Additionally, it must be also ensured that no application failures occur because the errors propagate. Depending on the harshness of the environment, different fault distribution and also fault probability has to be considered. As hardening, i.e. the implementation of mechanisms to detect and/or correct bugs, requires substantial resources on a chip, it is clear that domain and application-specific hardening is required. To keep the overhead low, Infineon has implemented an automated and scalable concept to harden a design. Since not hardening itself but its effects are subject to requirements - e.g. the percentage of detected bugs - the approach makes use of an automated analysis method as well. The talk introduces the concepts and reports about the experience using the automated hardening and analysis methods for a RISC-V core.


Safety development and verification flow for RISC-V cores

Maribel Gomez, Eyck Jentzsch, MINRES Technologies, DE

Abstract: The safety and reliability of a processor used in critical applications strongly depend on the quality and reliability of the development processes. At MINRES, we develop our RISC-V soft IP core family (TGC - The Good Core) according to the standard ISO 26262 Road vehicles - Functional safety, which covers the whole life cycle of electronic systems used in the automotive area. In this talk, we present our development and verification flow and how the safety aspects are integrated into the function-oriented and quality-oriented activities to produce trustworthy software-driven hardware.




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