Accepted papers

Sorted by IDs. All these papers will be published in formal proceedings indexed by IEEE Xplore (subject to the speaker registration and actual presentation of the paper at the symposium). 

Oral presentations:

Optimizing Packet Classification on FPGA
Kekely, Michal; Korenek, Jan

A Digital Delay Model Supporting Large Adversarial Delay Variations
Öhlinger, Daniel; Schmid, Ulrich

A Reliability-aware Environment for Design Exploration for GPU Devices
Limas Sierra, Robert Alexander; Guerrero Balaguera, Juan David; Rodriguez Condia, Josie Esteban; Sonza Reorda, Matteo

Evaluating the Hardware Performance Counters of Xtensa Virtual Prototype
Omotosho, Adebayo; Ilahi, Sirine; Villegas, Ernesto Cristopher; Hammer, Christian; Sauer, Christian

Felxible Neural Accelerator for Processing-in-Memory Architectures
Monavari, Ali; Fattahi, Sepideh; S. A. Rezaei, Hossein; Modarressi, Mehdi; Daneshtalab, Masoud

Split-Et-Impera: A Framework for the Design of Distributed Deep Learning Applications
Capogrosso, Luigi; Cunico, Federico; Lora, Michele; Cristani, Marco; Fummi, Franco; Quaglia, Davide

Standalone Area Optimized ASIC Tag Powered and Programmable by Light for Identification of Novel Drug Candidates
Korner, Dominic; Kramer, Andreas; Hofmann, Klaus; Hausch, Felix

Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoC with delay faults
Bernardi, Paolo; Filipponi, Gabriele; Sonza Reorda, Matteo; Appello, Davide; Bertani, Claudia; Tancorre, Vincenzo

Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree Models
Plambeck, Swantje; Fey, Goerschwin

A Lightweight Intrusion Detection System against IoT Memory Corruption Attacks
EL BOUAZZATI, Mohamed; TESSIER, Russell; TANGUY, Philippe; GOGNIAT, Guy

Resilence-Performance Tradeoff Analisys of Deep Neural Network Accelerator
Pappalardo, Salvatore; Ruospo, Annachiara; O'Connor, Ian; Deveautour, Bastien; Sanchez, Ernesto; Bosio, Alberto

MODEE-LID: Multiobjective Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia Classifiers
Hurta, Martin; Mrazek, Vojtech; Drahosova, Michaela; Sekanina, Lukas

Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques
Merten, Marcel; Hassan, Muhammad; Drechsler, Rolf

Verifying Bio-Electronic Systems
Heuer, Joseline; Krenz-Baath, Rene; Obermaisser, Roman

Prediction of Inference Energy on CNN Accelerators Supporting Approximate Circuits
Pinos, Michal; Mrazek, Vojtech; Sekanina, Lukas

Structured Design and Evaluation of a Resistor-Based PUF Robust Against PVT-Variations
Riehm, Carl; Frisch, Christoph; Burcea, Florin; Hiller, Matthias; Pehl, Michael; Brederlow, Ralf

Counterfeit Chip Detection using Scattering Parameter Analysis
Saadat Safa, Maryam; Mosavirik, Tahoura; Tajik, Shahin

A Comprehensive Analysis of Transient Errors on Systolic Arrays
Vacca, Eleonora; Azimi, Sarah; Sterpone, Luca

Reducing Output Response Aliasing Using Boolean Optimization Techniques
Hülle, Robert; Fišer, Petr; Schmidt, Jan

Active Wire Fences for Multi-Tenant FPGAs
Glamocanin, Ognjen; Kostic, Andela; Kostic, Stasa; Stojilovic, Mirjana

Poster presentations:

High-Throughput Approximate Multiplication Models in PyTorch
Trommer, Elias; Waschneck, Bernd; Kumar, Akash

LUTIC: A CRAM-based Architecture for Power Failure Resilient In-Memory Computing
Akhunov, Khakim; Yildirim, Kasim Sinan

Characterization of Interconnect Fault Effects in SRAM-based FPGAs
Fibich, Christian; Horauer, Martin; Obermaisser, Roman

Supporting analog design for reliability by efficient provision of reliability information to designers
Velarde Gonzalez, Fabio A.; Hahne, Lukas; Ortstein, Katrin; Lange, André; Crocoll, Sonja

HermesBDD: A Multi-Core and Multi-Platform Binary Decision Diagram Package
Capogrosso, Luigi; Geretti, Luca; Cristani, Marco; Fummi, Franco; Villa, Tiziano

A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators
Nosrati, Nooshin; Navabi, Zainalabedin

Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes
Krauss, Rune; Goli, Mehran; Drechsler, Rolf

Hardware Acceleration of FHEW
Bertels, Jonas; Van Beirendonck, Michiel; Turan, Furkan; Verbauwhede, Ingrid

Student paper presentations:

A Configurable Mixed-Precision Convolution Processing Unit Generator in Chisel
Vre?a, Jure; Biasizzo, Anton

APPRAISER: DNN Fault Resilience Analysis Employing Approximation Errors
Taheri, Mahdi; Ahmadilivani, Mohammad Hasan; Jenihhin, Maksim; Raik, Jaan; Daneshtalab, Masoud

Open Automation Framework for Complex Parametric Electrical Simulations
Vinagrero Gutierrez, Sergio; Inglese, Pietro; Vatajelu, Elena Ioana; Di Natale, Giorgio

A Low-Cost Combinational Approximate Multiplier
Hojati, Zahra; Navabi, Zainalabedin